The present invention relates to a timing signal generating circuit and a photographing device having the same circuit.
Digital still cameras and digital camcorders using a solid-state image pickup element including a CCD (Charge Coupled Device) and the like have a timing signal generating circuit for generating a plurality of kinds of timing signals for driving the solid-state image pickup element.
Recent cameras including this timing signal generating circuit have a plurality of kinds of photographing mode functions such as an auto focus mode, a high-speed shutter mode and the like in addition to an ordinary photographing mode.
The timing signal generating circuit therefore needs to generate a plurality of groups of the above-described plurality of kinds of timing signals for the respective photographing modes.
Known as a timing signal generating circuit for thus generating a plurality of kinds of timing signals is a timing signal generating circuit that has a memory therewithin, stores rising edge position data and falling edge position data of a plurality of kinds of timing signals to be generated in the memory in advance, and generates the plurality of kinds of timing signals using the rising edge position data and the falling edge position data stored in the memory (refer to, for example, Japanese Patent Laid-Open No. 2002-51270 (Patent Document 1)).
As shown in FIG. 7, this timing signal generating circuit 100 includes: a microcomputer interface 101 for receiving a control signal S100 input from a microcomputer; a RAM 102 for storing rising edge position data SET1 to SET4 and falling edge position data RST1 to RST4 of a plurality of timing signals S103 to be generated, on the basis of various setting signals S101 input from the microcomputer interface 101; and a pulse generator 103 for generating desired timing signals S103 using rising edge signals and falling edge signals S102 generated on the basis of the position data SET1 to SET4 and RST1 to RST4 stored in the RAM 102 as well as a vertical synchronizing signal VR and a horizontal synchronizing signal HR input from the microcomputer.
The RAM 102 forming the timing signal generating circuit 100 includes a plurality of mode areas M1 and M2 divided for each photographing mode and further includes, in each of the mode areas M1 and M2, a plurality of signal areas Va1 to Va8 divided for each of a plurality of timing signals S103 necessary in the mode.
All the signal areas Va1 to Va8 have eight timing storing areas n for storing pieces of rising edge position data SET1 to SET4 and falling edge position data RST1 to RST4 which pieces are equal in number to the number of pulses of the timing signal S103 having the largest number of pulses of all the timing signals S103 to be generated.
When the plurality of desired timing signals S103 are to be generated, the rising edge position data SET1 to SET4 and the falling edge position data RST1 to RST4 of the timing signals S103 are input to all the timing storing areas n. The pulse generator 103 combines the rising edge position data SET1 to SET4 and the falling edge position data RST1 to RST4 read from each of the signal areas Va1 to Va8, and thereby generates the plurality of desired timing signals S103.